Design Verification Engineer
We are looking for Senior Design Verification/Staff Design Verification Engineers who will be responsible for Design verification in module, subsystem and SOC along with developing verification IP, reference model based on UVM and Implement test with randomization based coverage driven verification methodology.
Key Responsibilities :
- Good experience of Design verification in module, subsystem and SOC.
- Develop verification IP and reference model based on UVM.
- Implement test with randomization based coverage driven verification methodology.
- Implement SVA, functional coverage, and finish functional/code coverage closure.
- Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
- IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
- Experience and debugging ability on SystemVerilog/UVM.
- Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
- Experience on Low Power and formal verification is a plus.
- UNIX scripting with Python, Perl, Makefile Cshell.
- Ability to work in teams or independently and quick to learn new technology.
- Bachelor or Master’s degree in Computer Science/Electrical & Electronics Engineering/IC design or related qualification.
- Should have 2-10 years verification experience.
- Should have strong communication and interpersonal skills.
Career LevelSenior ExecutiveQualificationBachelor’s Degree, Post Graduate Diploma, Professional Degree, Master’s DegreeYears of Experience2 yearsJob TypeFull-TimeJob SpecializationsEngineering, Electronics
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